1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for planarizing an insulating interlayer to be used in conjunction with other multilevel interconnect technology.
2. Description of the Related Art
In order to manufacture an integrated circuit, it is necessary to form many active devices on a single substrate. Initially, each of the devices must be isolated from the others, but recently it has become necessary to electrically interconnect specific devices during the fabrication step to obtain the desired functionality of the circuit. Both MOS and bipolar VLSI and ULSI devices have multilevel interconnect structures to accommodate the numerous interconnections of the devices.
As the number of layers in an interconnect structure increase, the topography of the top layer coated on the semiconductor wafer becomes more rugged. For example, in manufacturing a semiconductor wafer having two or more metal layers formed thereon, a first insulating interlayer is coated on the wafer on which a plurality of oxide layers, poly crystalline silicon conductive layers and a first metal wiring layer, have been previously formed, followed by forming vias for interposing a second metal layer. The surface of the first insulating layer is uneven because the underlying structure upon which the first insulating layer has been formed is uneven. When a second metal layer is directly formed over such a first insulating interlayer, the second metal layer fractures due to peaks and/or cracks in the first insulating interlayer and, as a result, the metal coverage over the first insulating interlayer fails. This failure lowers the yield of the semiconductor device. Therefore, planarization of the insulating interlayer is required for multilevel metal interconnections, before forming a via or coating a second metal layer.
One of the simplest methods available for planarizing the semiconductor wafer having steps formed thereon is to deposit a CVD-glass layer which is significantly thicker than the step height it must cover. However, this is unrealistic because increasing the thickness of the insulating layer also increases the via depth between a first metal wiring layer and a second metal layer. Furthermore, as the first metal wiring layers become more closely packed, voids will form in the insulating layer if conventional CVD-SiO.sub.2 processes are used.
One conventional planarization method as described by S. Wolf in Silicon Processing for the VLSI Era. Vol. 2, to form an exemplary insulating layer includes using a resist layer coated on an insulating interlayer as a sacrificial layer. The process comprises coating a resist layer and etching back the insulating interlayer by using the resist layer as a sacrificial layer to adjust the thickness of the insulating interlayer.
In the next step, the sacrificial resist layer is first rapidly etched back by dry etching until the topmost regions of the insulating interlayer are just barely exposed. The etch chemistry is then modified so that the sacrificial layer material and the insulating interlayer material are etched at approximately the same rate. Etching continues under these conditions until all of the sacrificial resist layer has been etched away. By this etch-back procedure, the surface of the insulating interlayer is highly planarized since the profile of the sacrificial layer is thus transferred to the insulating interlayer. In some cases, the thickness of the insulating interlayer over underlying metal layers may be thinner than desired after the etch-back step is completed. In other cases, etch-back is allowed to proceed until the first metal wiring layers are exposed for improving the degree of planarization. In such a case, an additional CVD insulating layer is generally deposited in order to establish the minimum adequate thickness of the insulating interlayer.
With the increase in integration density of semiconductor devices, the spaces between the metal layers become narrower. Therefore, various problems such as the formation of voids in the insulating interlayer occur, so its planarization becomes difficult to improve. To improve the degree of planarization of the insulating layer formed over such closely spaced metal layers, a method of repeating the etch-back step two times has been typically carried out.
FIGS. 1A to 1D illustrate a process for planarizing an insulating interlayer by two times etch-back.
FIG. 1A displays a first metal wiring layer 2 which has been formed on a semiconductor substrate 1 with a pattern as shown. A CVD-SiO.sub.2 layer 3 is formed on the first metal wiring layer 2 and the semiconductor substrate 1 as illustrated in the figure. The final stage demonstrated in FIG. 1A is the formation of a resist layer 4 on top of the CVD-SiO.sub.2 layer 3.
FIG. 1B demonstrates results of a first etching back-step of the resist layer 4 and the CVD-SiO.sub.2 layer 3 shown in FIG. 1A. A CVD-SiO.sub.2 layer 3a with spaces 9 between the first metal wiring layer 2 is the result of the first etching back-step. The spaces between the first metal wiring layer 2 are an undesirable side effect of the first etching back as will be discussed later.
FIG. 1C shows the effect of forming a second CVD-SiO.sub.2 layer 5 upon the CVD-SiO.sub.2 layer 3a shown in FIG. 1B. The CVD-SiO.sub.2 layer 5 is formed in the same manner as was the CVD-SiO.sub.2 layer 3a, thereby forming voids 7 in the spaces 9. A second resist layer 6 is then formed on the second CVD-SiO.sub.2 layer 5 with the same techniques uses to form resist layer 4.
FIG. 1D demonstrates the results of a second etching back step of the second resist layer 6 and the second CVD-SiO.sub.2 layer 5 shown in FIG. 1C. A planarized insulating layer 3b comprising CVD-SiO.sub.2 is shown in this illustration with a planar top surface 8 and voids 7 which are the product of the second etching back step. A third CVD-SiO.sub.2 layer (not shown in the drawings) may be formed on the planarized insulating layer 3b if the planarized insulating layer 3b does not meet minimum thickness specifications.
Accordingly, as exemplified, a planarized insulating interlayer 3 containing voids 7 may be fabricated. Trouble arises when the first CVD-SiO.sub.2 layer 3 is formed and etched back by using a sacrificial resist layer 4. The first etch back generates negative-sloped spaces 9 in the first CVD-SiO.sub.2 layer 3a making further layer formations difficult at the negative sloped spaces 9. Therefore, the formation of the second CVD-SiO.sub.2 layer 5 contains undesirable voids 7.